1. Field of the Invention
The present invention relates in general to a transceiver for concurrently transmitting and receiving signals representing data sequences via the same communication channel, and in particular to a system for reducing effects of a residual echo of the transceiver's transmitted signal within the transceiver's received signal on data sequences the transceiver derives by processing its incoming signal.
2. Description of Related Art
FIG. 1 illustrates a conventional full duplex transceiver 10 for concurrently transmitting and receiving data via analog signals over the same bi-directional transmission line or other type of channel 12. Transceiver 10 converts an input data sequence tx(n) into an outgoing analog signal z(t) transmitted to a remote transceiver (not shown) via channel 12, and processes an analog incoming signal y(t) arriving on channel 12 from the remote transceiver to produce an output data sequence rx(n) matching a data sequence incoming signal y(t) represents.
Transceiver 10 includes an encoder 14 for encoding input data sequence tx(n) into another digital data sequence x(n) indicating the time-varying behavior outgoing signal z(t) must exhibit to represent sequence x(n). A digital-to-analog converter (DAC) 16 converts data sequence x(n) into an analog signal x(t), a line driver 18 amplifies the x(t) signal to produce a signal r0(t), and a hybrid circuit 20 for transmits the outgoing z(t) signal on channel 12 in response to the r0(t) signal.
Hybrid circuit 20 also generates an analog output signal r(t). A variable gain amplifier 21 amplifies the r(t) signal to produce an analog signal r′(t), a low-pass filter (LPF) 22 filters r′(t) to produce an analog “received” signal p(t), and an analog-to-digital converter 24 digitizes the p(t) signal to generate a digital waveform data sequence u(n) representing the behavior of the incoming signal y(t). A summer 26 subtracts a sequence v(n) produced by a digital echo cancellation circuit 27 from the u(n) sequence to produce a sequence w(n) supplied to an equalizer 28, which processes the w(n) sequence to generate a “soft decision” sequence s(n). Data elements of soft decision sequence s(n) represent approximately the same values as corresponding elements of the remote transceiver's x(n) sequence controlling behavior of incoming signal y(t) but with higher resolution. A slicer 30 reduces the resolution of soft decision sequence s(n) to produce a hard decision sequence h(n) matching the remote transceiver's x(n) sequence. A decoder 32 decodes hard decision sequence h(n) to produce the transceiver's output data sequence rx(n) which matches the remote transceiver's input tx(n) sequence.
Outgoing signal z(t) represents data sequences by periodically transitioning between a set of discrete voltage levels in an order controlled by the local transceiver's x(n) sequence. Since incoming signal y(t) is the remote transceiver's outgoing signal, it will also nominally transition between the same set of discrete voltage levels in an order specified by the remote transceiver's x(n) sequence. Since channel 12 attenuates incoming signal y(n), an automatic gain control circuit 31 monitors the u(n) sequence output of ADC 24 and adjusts the gain of amplifier 21 to compensate for the attenuation of the incoming signal. A timing recovery circuit 32 monitors soft and hard decision sequences s(n) and h(n) to determine how to control the phase and frequency of the ADC's sampling clock (CLOCK) so that ADC 24 periodically digitizes the p(t) signal at the appropriate times between its level transitions. Equalizer 28, suitably implemented by a finite impulse response filter, adjusts soft decision s(n) to compensate for inter symbol interference (ISI) distortion in the y(t) signal. An equalization adaptation circuit 34 monitors sequences h(n), s(n) and w(n) to determine how to adjust filter coefficients controlling equalizer 28 so that the equalizer correctly compensates for ISI distortion.
FIG. 2 illustrates line driver 18 and hybrid circuit 20 of FIG. 1 in more detailed block diagram form. Line driver 18 amplifies x(t) to produce the analog signal r0(t) and hybrid circuit 20 couples the r0(t) signal to channel 12 through a resistor R1 to produce outgoing signal z(t). Resistors R2 and R3 couple the inverting input of summing amplifier 40 between the output of line driver 18 and ground to produce a signal r2(t) at the inverting input that is a replica of outgoing signal z(t). Channel 12 is also connected to a non-inverting input of a summing amplifier 40 which generates the r(t) signal supplied to amplifier 21 of FIG. 1. A combined signal r1(t) appearing at the non-inverting input of summing amplifier 40 is of magnitude equal to the sum of magnitudes of outgoing signal z(t) and incoming signal y(t),r1(t)=z(t)+y(t)Ideally the replica signal r2(t) appearing at the inverting input of summing amplifier 40 will match the z(t) component of the r1(t) signal in both phase and amplitude so that when amplifier 40 offsets r1(t) with r2(t), summing amplifier 40 will remove all of the echo of both the outgoing signal z(t) and its replica r2(t) from the hybrid circuit's output signal r(t) so that r(t) will be an accurate representation of incoming signal y(t). Accordingly,whenr2(t)=z(t) andr1(t)=z(t)+y(t)thenr(t)=r1(t)−r2(t) =[z(t)+y(t)]−z(t) =y(t).Thus hybrid circuit 20 ideally cancels z(t) from r(t) to produce a received signal r(t) matching incoming signal y(t). However since the replica signal r2(t) will never exactly match the z(t) component of r1(t) either in amplitude or in phase, it will not entirely cancel the effects of outgoing signal z(t) on received signal r(t). Some amount of residual echo of outgoing signal z(t) will therefore appear as a component of the hybrid circuit's output signal r(t) and can affect the digital waveform data sequence u(n) output of ADC 24 of FIG. 1.
Digital echo cancellation circuit 27 of FIG. 1 processes the x(n) sequence controlling the z(t) sequence to generate a sequence v(n) approximating the residual echo appearing in the u(n) sequence so that when summer 26 subtracts the v(n) sequence from the u(n) sequence, it removes much of the residual echo from the resulting w(n) sequence. An adaptation circuit 36 monitors hard and soft decision sequences h(n) and s(n) to determine how to adjust filter coefficients controlling the manner in which echo cancellation circuit 27 estimates the residual echo.
While echo cancellation circuit 27 is able to adequately compensate for small amounts of residual echo in the u(n) sequence arising from differences in amplitude of outgoing signal z(t) and its replica signal r2(t), it is less adept at compensating for residual echo peaks in the u(n) sequence arising from phase differences between the z(t) and r2(t) signals. Phase differences between the z(t) component of r1(t) and its replica r2(t) arise due to differences in signal path delays from the output of line driver 18 to the inverting and non-inverting inputs of summing amplifier 40. The path delays are functions of path length and impedances and it is difficult to precisely match the delays of the two signal paths, particularly in high frequency applications where small differences in path impedances can result in relatively large phase differences.
FIG. 3 is a timing diagram illustrating an example of the manner in which various signals of FIGS. 1 and 2 may behave. Clock signals controlling operations of the local and remote transceivers are synchronized to the extent that level transitions in the x(t) and y(t) signal components of the r1(t) signal and the level transitions in replica signal r2(t) all occur with the same frequency, but they do not necessarily occur at the same time when viewed at the inputs of summing amplifier 40. In the example illustrated in FIG. 3, the r2(t) and z(t) signal components r1(t) have the same magnitude but differ in phase. The magnitude difference between r2(t) and z(t) peaks during times when r2(t) and z(t) transition and those peaks appear as residual echo components of the r(t) signal input to amplifier 21 of FIG. 1.
The “received” signal p(t) supplied as input to ADC 24 of FIG. 1 is an amplified and filtered version of r(t) and ideally should have an amplitude proportional to y(t). Timing recovery circuit 32 of FIG. 1 adjusts the phase and frequency of the CLOCK signal input to ADC 24 so that the ADC samples p(t) between its transitions. In this particular example, the residual noise peaks in p(t) resulting from the phase difference in between the r2(t) and z(t) signals happen to occur when received signal p(t) is being sampled, and in such case the residual noise due to the phase difference between r2(t) and z(t) has a substantial effect on the value of the u(n) sequence output of ADC 24.
It is possible to reduce the residual echo peaks by reducing differences in path delays between the output of driver 18 and the inverting and non-inverting inputs of summing amplifier 40 so as to reduce the phase difference between r2(t) and z(t). But adjusting signal paths delays to substantially eliminate such phase differences can be difficult, particularly in high frequency applications where very small differences in signal path lengths or impedances can substantially affect phase differences between the r2(t) and z(t) signals. Therefore what is needed is a way to reduce the effect on the output u(n) sequence of ADC 24 of residual echo peaks in the r(t) signal arising from a phase mismatch between the z(t) component of r1(t) and replica signal r2(t).